Boost schemes for write assist

ABSTRACT

A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a division of U.S. patent application Ser. No.16/662,433, titled “BOOST SCHEMES FOR WRITE ASSIST” filed Oct. 24, 2019,the disclosure of which is hereby incorporated herein by reference inits entirety, and claims priority to U.S. Provisional Patent ApplicationNo. 62/753,760 titled “BOOST SCHEMES FOR SRAM WRITE ASSIST” filed Oct.31, 2019, the disclosure of which is also hereby incorporated byreference in its entirety.

BACKGROUND

A common type of integrated circuit memory is a static random accessmemory (SRAM) device. A typical SRAM memory device includes an array ofbit cells, with each bit cell having six transistors connected betweenan upper reference potential and a lower reference potential. Each bitcell has two storage nodes where information may be stored. The firstnode stores the desired information, while the complementary informationis stored at the second storage node. SRAM cells have the advantageousfeature of holding data without requiring a refresh.

The lowest VDD voltage (positive power supply voltage) at which an SRAMbit cell may function is referred to as Vccmin. Having a low cell VDDnear Vccmin reduces leakage current and also reduces the incidence ofread flips. But having a high cell VDD improves the probability ofsuccessful write operations. Therefore, the Vccmin is limited by thewrite operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a schematic diagram of a device with a first boost circuit inaccordance with some embodiments.

FIG. 2 is a graph illustrating the modeled results of using the firstboost circuit in accordance with some embodiments.

FIG. 3 is a schematic diagram illustrating aspects of an alternativeembodiment of the first boost circuit in accordance with someembodiments.

FIG. 4 is a schematic diagram of a device with a second boost circuit inaccordance with some embodiments.

FIG. 5 is a schematic diagram illustrating aspects of an alternativeembodiment the second boost circuit in accordance with some embodiments.

FIG. 6 is a schematic diagram illustrating a first exampleimplementation of metal capacitors in accordance with some embodiments.

FIG. 7 is a schematic diagram illustrating a second exampleimplementation of metal capacitors in accordance with some embodiments.

FIG. 8 is a schematic diagram illustrating a third exampleimplementation of metal capacitors in accordance with some embodiments.

FIGS. 9A, 9B, and 9C are schematic diagrams illustrating a fourthexample implementation of metal capacitors in accordance with someembodiments.

FIGS. 10A and 10B are schematic diagrams illustrating different lengthsfor metal stripes of metal capacitors for the first boost circuit inaccordance with some embodiments.

FIG. 10C a graph illustrating the modeled results of the differentlengths for metal stripes of metal capacitors the first boost circuit inaccordance with some embodiments.

FIG. 10D a graph illustrating the modeled results of power consumptionfor write assist operation using different lengths for metal stripesforming metal capacitors of the first boost circuit in accordance withsome embodiments.

FIGS. 11A and 11B are schematic diagrams illustrating different lengthsfor metal stripes of metal capacitors of the second boost circuit inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The disclosure provides boost circuits that enables a more balancednegative bit line voltage (“NVSS”) across a plurality of memory cellsconnected to the bit line for optimizing write performance whileminimizing the impact on transistor reliability. In addition, thedisclosure provides boost circuits that enable a more balanced boostvoltage (“BVDD”) across a plurality of memory cells connected to a wordline for optimizing write performance while minimizing the impact ontransistor reliability. This is advantageous for a number of circuit onchip devices, as well as other circuits, including for example SRAMmemory arrays. Embodiments constructed in accordance with the principlesof the present invention provide improved write assist.

FIG. 1 illustrates a device 100 having a first boost circuit, inaccordance with some embodiments. Device 100 may be a circuit having amemory device, such as a SRAM device. Device 100 includes a first boostcircuit (also referred to as a bit line boost circuit 102) coupled to awrite driver circuit 104. Device 100 further includes a cell array 112and a word line driver circuit 114. Cell array 112 includes a pluralityof bit cells arranged in matrix of plurality of rows and columns. Eachof the plurality of rows include a first plurality of bit cells and eachof the plurality of columns include a second plurality of bit cells.Each of the first plurality of bit cells of each of the plurality ofrows are connected to one of a plurality of word lines and each of thesecond plurality of bit cells of each of the plurality of columns areconnected to a pair of bit lines (that is a bit line and an inverse bitline (BL/BLB)). Each bit cell of cell array 112 is configured as a pairof cross-coupled invertors that operate to reinforce the data statestored therein, i.e., the true data node reinforces the complementarydata node and vice versa. That is, each bit cell of cell array 112 isconfigured to store one bit of information (that is, bit value of 0 or1).

Word line driver circuit 114 is operative to select one of the pluralityof word lines (that is WL1, . . . , WLn) and charge the selected wordline to a predetermined voltage. Write driver circuit 104 is operativeto write one bit of information to bit cells connected to the selectedone of the plurality of word lines. Write driver circuit 104 includes afirst invertor (INV1) coupled to a bit line (BL) through a write columnmultiplexer selection transistor (N2) and a second invertor (INV2)coupled to the inverse bit line (BLB) through a write column multiplexertransistor (N3). The illustrated figure shows a logical “0” beingwritten into the data node of a bit cell through driver INV1. As such, alogical “0” is written into the complementary data node through driverINV2.

Bit line boost circuit 102 is operative to assist the write operationsin cell array 112. For example, bit line boost circuit 102 is operativeto optimize the write Vccmin performance while minimizing the impact ontransistor reliability. In example embodiments, bit line boost circuit102 may be coupled either to a near-end or a far end of the pair of bitlines (BL/BLB). The near-end of the pair of bits lines is an end closerto write driver circuit 104 and the far-end is an end away from writedriver circuit 104, or vice versa.

Bit line boost circuit 102 includes a first metal capacitor C1 106, afirst logic device 108, and a discharge device N1 110. A boost signal isconnected to an input of first logic device 108. First logic device 108is operative to invert the boost signal. The output of first logicdevice 108 is connected to a gate of discharge device N1 110 at a node2. In example embodiments, first logic device 108 is an invertorcircuit, for instance, a NOT logic gate. However other types of logicgates are within the scope of the disclosure.

Discharge device N1 110 is connected between a first node (also referredto as node 1) which is the origin of the ground of the BL discharge pathand the ground (VSS). In example embodiments, discharge device N1 110 isa transistor, for example, an n-channel metal-oxide semiconductor (nMOS)transistor. However, other types of transistors are in the scope of thedisclosure. First metal capacitor C1 106 is connected between the node 1and the node 2, that is, between the gate of discharge device N1 110 andthe NVSS. First metal capacitor C1 106 of bit line boost circuit 102 isdiscussed in greater detail with respect for FIGS. 6, 7, 8, 9A, 9B, 9C,10A, 10B, 10C, and 10D of the disclosure.

In example embodiments, the boost signal may be linked with write enablesignal and be responsive to the write enable signal. A boost signalcircuit (not shown) may be provided to generate the boost signal whichis linked to the write enable signal. For example, when the write enablesignal changes to a logic high indicating initiation of the writeoperation, the boost signal may also change to a logic high. Inaddition, when the write enable signal changes to a logic low indicatingan end of the write operation, the boost signal may change to a logiclow. In some examples, the write enable signal is delayed by apredetermined time to provide the boost signal.

During write operations, before the write enable signal changes to alogic high (at the start of the write operation/period), the boostsignal is at a logic low. Hence, the node 2 of bit line boost circuit102 is at logic high, which turns discharge device N1 110 on and chargesfirst metal capacitor C1 106. In addition, when the boost signal is at alogic low, the node 1 is also connected to ground through dischargedevice N1 110.

When the write enable signal changes to a logic high (at the start ofthe write operation/period), the boost signal also changes to a logichigh, which turns off discharge device N1 110 and, at the same time,causes a discharge from first metal capacitor C1 106, which drives avoltage of the node 1 from the ground to a negative value. This negativevoltage is provided to the pair of bit lines (BL/BLB), which provides aboost for the write operation performed to bit cells coupled to the bitlines (BL/BLB).

FIG. 2 is a graph illustrating modeled results 200 of using first metalcapacitor C1 106 in comparison with using a MOS capacitor for differentoperating voltages of cell array 112. For example, first plot 202illustrates the modeled results of only using first metal capacitor 106in a far end bit line boost circuit 102 for different operating voltagesof cell array 112. Moreover, second plot 204 illustrates the modeledresults of only using first metal capacitor C1 106 in a near-end bitline boost circuit 102 for different operating voltages of cell array112. Furthermore, third plot 206 illustrates the modeled results of onlyusing a MOS capacitor in a far-end write assist circuit for differentoperating voltages of cell array 112. Lastly, fourth plot 208illustrates the modeled results of only using a MOS capacitor in anear-end write assist circuit for different operating voltages of cellarray 112.

The graph illustrates that by using only a MOS capacitor the near-endresults in a negative bit line voltage value are greater than thefar-end values (as illustrated on the Y-axis). This result occursregardless of the operating voltage of cell array 112 (as illustrated onthe x-axis). However, the difference is more pronounced (e.g., Near>Far)as the operating voltage increases. In contrast by using first metalcapacitor C1 106 in a far-end-write-assist circuit, the far-end resultsare more negative than the near-end. Again, this result occursregardless of the operating voltage of cell array 112. However, thedifference is greater (e.g., Far>Near) as the operating voltageincreases.

FIG. 3 illustrates device 100 with an alternative embodiment of bit lineboost circuit 102′ in accordance with some embodiments. In thisalternative embodiment, in addition to first metal capacitor C1 106, afirst MOS capacitor 302 is added in parallel to first metal capacitor C1106. Adding first MOS capacitor 302 in parallel to first metal capacitorC1 106 may reduce the real estate requirements of first metal capacitorC1 106.

FIG. 4 illustrates device 100 with a second boost circuit in accordancewith example embodiments. As shown in FIG. 4, device 100 includes asecond boost circuit (also referred to as a word line boost circuit402). Word line boost circuit 402 is coupled to word line driver circuit114. As stated above, during the write operations, word line drivercircuit 114 is operative to select one of the plurality of word lines ofcell array 112 and charge the selected one of the plurality of wordlines to a predetermined voltage. Word line boost circuit 402 isoperative to boost the charge on the selected one of the plurality ofword lines to assist in write operations in cell array 112. Word lineboost circuit 402 is connected to word line driver circuit 114 at a node3, also referred to as a boost node.

Word line boost circuit 402 includes a second metal capacitor C2 406, afirst transistor P1 408, and a second transistor P2 410. Firsttransistor P1 408 and second transistor P2 410 are connected between theVDD and the node 3. Gate of first transistor P1 408 is connected to anode 4. Gate of second transistor P2 410 is connected to the node 3.Second metal capacitor C2 406 is connected between the node 3 and thenode 4. Boost signal is connected to a first place of second metalcapacitor C2 406 through the node 4. First transistor P1 408 is alsoreferred to as a pre-charge device. In example embodiments, firsttransistor P1 408 and second transistor P2 410 may be p-channel MOStransistors. However, other types of transistors are within scope of thedisclosure. Second metal capacitor C2 406 is discussed in greater detailwith respect to FIGS. 6, 7, 8, 9A, 9B, 9C, 11A, and 11B of thedisclosure.

During operation, when the boost signal changes to a logic high, firsttransistor P1 408 is turned off which disconnects the node 3 from theVDD. In addition when the boost signal changes to a logic high, secondmetal capacitor C2 406 is charged to a voltage higher than the VDD.Hence, the voltage at the node 3 is boosted to a voltage higher than theVDD (that is, to a boosted VDD (BVDD)). The boosted voltage (BVDD) isthen provided to the selected one of the plurality of word lines viaword line driver circuit 114. The boosted voltage may assist in thewrite operations in cell array 112.

FIG. 5 illustrates device 100 with an alternative embodiment of wordline boost circuit 402′ is in accordance with some embodiments. In thisalternative embodiment, a second MOS capacitor 502 is added in parallelto second metal capacitor C2 406. Adding second MOS capacitor 502 inparallel to second metal capacitor C2 406 reduces the real estaterequirements of second metal capacitor C2 406.

FIG. 6 illustrates a first example implementation 600 of first metalcapacitor C1 106 and second metal capacitor C2 406 in accordance withsome embodiments. In first example implementation 600, the metalcapacitors are formed using two substantially parallel metal plates intwo metal layers separated by a dielectric material. A first metal plateof the two substantially parallel metal plates which is formed in afirst metal layer is connected to a first node. A second metal plate ofthe two substantially parallel metal plates which is formed in a secondmetal layer, which is different from the first metal layer of the firstmetal plate, is connected to a second node, thereby, forming a capacitorbetween the first node and the second node. A capacitance value in firstexample implementation 600 is varied by varying dimensions of the metalplates.

For example, and as shown in FIG. 6, first example implementation 600includes a first metal plate 602 and a second metal plate 604substantially parallel to first metal plate 602. First metal plate 602is formed in the metal 3 layer and second metal plate 604 is formed inthe metal 4 layer. First metal plate 602 is connected to a first metalline 606 which is connected to a first node (that is, Node A) and secondmetal plate 604 is connected to a second metal line 608 through a via610. Second mental line 608 is connected to a second node (that is, NodeB) thereby forming a capacitor between Node A and Node B. Node A andNode B be can be one of node 1, node 2, node 3, and node 4 of memorydevice 100. A capacitance value in first example implementation 600 isconfigurable to a desired capacitance value by configuring dimensions offirst metal plate 602 and second metal plate 604.

First metal line 608 and second metal line 610 are also formed in ametal 3 layer. Second metal plate 604 is substantially parallel to firstmetal plate 602 and is separated from first metal plate 602 by apredetermined gap. In example embodiments, the predetermined gap can befilled with a dielectric material. The dielectric material may includemay be a polymer such as polybenzoxazole (PBO), polyimide,benzocyclobutene (BCB), or the like; a nitride such as silicon nitrideor the like; an oxide such as silicon oxide, PhosphoSilicate Glass(PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass(BPSG), or the like; the like, or a combination thereof. However, othertypes of dielectric materials are within scope of the disclosure.

Although first metal plate 602 is shown to be formed in metal 3 layerand second metal plate 604 is shown to be formed in metal 4 layer, othermetal layers are within scope of the disclosure for both first metalplate 602 and second metal plate 604. In addition, although first metalline 608 and second metal line 610 are shown be formed in the same metallayer as first metal plate 602 (that is, metal 3 layer), it will beapparent to a person with ordinary skill in the art after reading thisdisclosure that first metal line 608 and second metal line 610 can beformed in the same metal layer as second metal plate 604 (that is, metal4 layer). Dimensions and shapes of each of first metal plate 602 andsecond metal plate 604 can be based on a desired capacitance value.

In example embodiments, a first metal layer (also referred to as a metal1 layer) is generally the lowest metal layer in an integrated circuit(IC). That is, the metal 1 layer is the metal layer closest to asubstrate on which the metal layers are formed. A second metal layer(also referred to as a metal 2 layer) is the metal layer formed abovethe metal 1 layer without any other metal layer between the metal 1layer and the metal 2 layer. Likewise, a third metal layer (alsoreferred to as the metal 3 layer) is the next metal layer formed abovethe metal 2 layer without any other metal layer between the metal 2layers and the metal 3 layer. Similarly, a fourth metal layer (alsoreferred to as the metal 4 layer) is the next metal layer formed abovethe metal 3 layer without any other metal layer between the metal 3layers and the metal 4 layer. The progression of metal layers continuesin this fashion until a top metal layer is formed, for example, theeighth metal layer (also referred to as metal 8 layer) formed above aseventh metal layer (also referred to as metal 7 layer) without anyother metal layer between the metal 7 layer and the metal 8 layer. It isto be understood that the disclosure is not limited to any specificnumber of metal layers.

FIG. 7 illustrates a second example implementation 700 of first metalcapacitor C1 106 and second metal capacitor C2 406 in accordance withsome embodiments. Second example implementation 700, which is alsoreferred to as hand clasping style, includes two sub-capacitors, that isa first sub-capacitor and a second sub-capacitor, formed in parallel toeach other. The two sub-capacitors are formed from two sets of metalstripes. For instance, a first sub-capacitor is formed from a first setof metal stripes and a second sub-capacitor is formed parallel to thefirst sub-capacitor from a second set of metal stripes. First set ofmetal stripes are placed parallel to each other thereby forming acapacitor between each two consecutive metal stripes. Similarly, secondset of metal stripes are also placed parallel to each other therebyforming a capacitor between each two consecutive metal stripes. Acapacitance value of each of the two sub-capacitors is dependent on anumber of metal stripes and dimensions of metal stripes in eachcorresponding set of metal stripes and a length of each metal stripes.An overall capacitance value in second example implementation 700 isdetermined as sum of the two sub-capacitors formed by the two set ofmetal stripes.

For example, and as shown in FIG. 7, second example implementation 700includes a first sub-capacitor formed from a first set of metal stripes702 and a second sub-capacitor formed from a second set of metal stripes704. Each of a first set of metal stripes 702 and second set of metalstripes 704 are formed in two different metal layers. For example, firstset of metal stripes 702 are formed in a metal 2 layer and second set ofmetal stripes 704 formed in a metal 4 layer. However, other metal layersare within the scope of disclosure.

Continuing with FIG. 7, the first sub-capacitor is formed between afirst pair of metal lines (that is, a first metal line 706 and a secondmetal line 708). Each of first metal line 706 and second metal line 708are formed in metal 1 layer and form a path 1. Moreover, each of firstset of metal stripes 702 are connected to first metal line 706 or secondmetal line 708 in alternate through a via. Second sub-capacitor isformed between a second pair of metal lines (that is, a third metal line710 and a fourth metal line 712). Each of third metal line 710 andfourth metal line 712 are formed in metal 3 layer and form a path 2.Each of second set of metal stripes 704 are connected to third metalline 710 or fourth metal line 712 in alternate through a via. Firstmetal line 706 and third metal line 710 are connected to a first node(that is, Node A), and second metal line 708 and fourth metal line 712are connected to a second node (that is, Node B) thereby forming acapacitor between Node A and Node B. Node A and Node B be can be one ofnode 1, node 2, node 3, and node 4 of memory device 100.

Each of first set of metal stripes 702 and second set of metal stripes704 include a predetermined number of metal stripes placed parallel toeach other. A capacitor is formed between each two consecutive metalstripes. A total capacitance value for each of first set of metalstripes 702 and second set of metal stripes 704, thus, is dependent upona number of metal stripes and dimensions of metal stripes in acorresponding set. For example, first set of metal stripes 702 includesthree metal stripes and second set of metal stripes 704 includes sevenmetal stripes. However, a number of metal stripes for each of first setof metal stripes 702 and second set of metal stripes 704 may vary basedon a desired capacitance value of each of the first sub-capacitor andthe second sub-capacitor. Hence, a different number of metal stripes foreach of first set of metal stripes 702 and second set of metal stripes704 is within the scope of the disclosure. In addition, the dimensionsof each metal stripes of first set of metal stripes 702 and second setof metal stripes 704 may also may vary based on a desired capacitancevalue of the first sub-capacitor and the second sub-capacitor.

In example implementations, each metal stripes of first set of metalstripes 702 are parallel to each other with gaps between the stripesbeing filled with a dielectric material. Similarly, each metal stripesof second set of metal stripes 704 are parallel to each other with gapsbetween the stripes being filled with a dielectric material. An exampledielectric material can include a polymer such as polybenzoxazole (PBO),polyimide, benzocyclobutene (BCB), or the like; a nitride such assilicon nitride or the like; an oxide such as silicon oxide,PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-dopedPhosphoSilicate Glass (BPSG), or the like; the like, or a combinationthereof. However, other dielectric materials are within scope of thedisclosure.

In other example implementation, one of the first sub-capacitor and thesecond sub-capacitor can be selectively de-activated. For example, oneof the first sub-capacitor and the second sub-capacitor can beselectively de-activated disconnecting it from the boost signal path(that is, disconnecting path 1 or path 2). The one of the firstsub-capacitor and the second sub-capacitor can be selectivelyde-activated to vary the desired capacitance value. In other exampleimplementation, each of path 1 or path 2 may include a switches (notshown) which are operative to selectively activate each of the firstsub-capacitor and the second sub-capacitor respectively.

FIG. 8 illustrates a third example implementation 800 of first metal C1106 and second metal capacitor C2 406 in accordance with someembodiments. Third example implementation 800, which is also referred toas a grid style, includes three set of metal stripes. Each of the threeset of metal stripes form three sub-capacitors. For example, a firstsub-capacitor is formed from a first set of metal stripes placedparallel to each other, a second sub-capacitor is formed from a secondset of metal stripes placed parallel to each other, and a thirdsub-capacitor is formed from a third set of metal stripes placedparallel to each other. Each successive metal stripe of each of thefirst set of metal stripes and the second set of metal stripes areconnected to metal stripes of the third set of metal stripes inalternate thereby forming a grid. A capacitance value of each of thethree sub-capacitors is dependent on a number of metal stripes in eachcorresponding set of metal stripes and dimensions of each metal stripes.An overall capacitance value in third example implementation 800 isdetermined as sum of the three sub-capacitors formed by the three set ofmetal stripes.

For example, and as shown in FIG. 8, third implementation 800 includes afirst set of metal stripes 802, a second set of metal stripes 804, and athird set of metal stripes 806. Third metal set of stripes 806 may beplaced in a first direction, and first set of metal stripes 802 andsecond set of metal stripes 804 may each be formed in a seconddirection. The second direction may be orthogonal to the firstdirection. Each metal stripe of first set of metal stripes 802 and eachmetal stripe of second set of metal stripes 804 are connected to eachalternate metal stripe of third set of metal stripes 806 through a viaforming a grid. That is, a first metal stripe of each of first set ofmetal stripes 802 and second set of metal stripes is connected to asecond, fourth, sixth, . . . , metal stripe of third set of metalstripes 806. And, a second metal stripe of each of first set of metalstripes 802 and second set of metal stripes is connected to a first,third, fifth, . . . , metal stripe of third set of metal stripes 806.

A capacitor is formed between two adjacent pair of metal stripes of eachof first set of metal stripes 802, second set of metal stripes 804, andthird set of metal stripes 806. A capacitance value for each of thefirst sub-capacitor formed by first set of metal stripes 702, the secondsub-capacitor formed by second set of metal stripes 704 and the thirdsub-capacitor formed by third set of metal stripes 706 is dependent upona number of metal stripes in each set and dimensions of each metalstripes. Hence, each of first set of metal stripes 802, second set ofmetal stripes 804, and third set of metal stripes 806 include apredetermined number of metal stripes. For example, first set of metalstripes 802 includes three metal stripes, second set of metal stripes804 includes seven metal stripes, and third set of metal stripes 806includes six metal stripes. However, a number of metal stripes in eachof first set of metal stripes 802, second set of metal stripes 804, andthird set of metal stripes 806 may vary based on a desired capacitancevalue. Hence, a different number of metal stripes for each of first setof metal stripes 802, second set of metal stripes 804, and third set ofmetal stripes 806 is within the scope of the disclosure. In addition, adimension of the metal stripes of in each of first set of metal stripes802, second set of metal stripes 804, and third set of metal stripes 806may vary based on a desired capacitance value. One stripe of third setof metal stipes 806 is connected to a first node (that is, Node A) andanother stripe of third set of metal stripes 806 is connected to asecond node (that is, Node B) thereby forming a capacitor between Node Aand Node B. Node A and Node B be can be one of node 1, node 2, node 3,and node 4 of memory device 100.

Each metal stripe of first set of metal stripes 802 are parallel to eachother with gaps between the metal stripes being filled with a dielectricmaterial. Similarly, each metal stripes of second set of metal stripes804 are parallel to each other with gaps between the stripes beingfilled with a dielectric material. Additionally, each metal stripes ofthird set of metal stripes 806 are parallel to each other with gapsbetween the stripes being filled with a dielectric material. An exampledielectric material can include a polymer such as polybenzoxazole (PBO),polyimide, benzocyclobutene (BCB), or the like; a nitride such assilicon nitride or the like; an oxide such as silicon oxide,PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-dopedPhosphoSilicate Glass (BPSG), or the like; the like, or a combinationthereof. However, other dielectric materials are within scope of thedisclosure.

In addition, each of first set of metal stripes 802, second set of metalstripes 804, and third set of metal stripes 806 can be different metallayers. For example, first set of metal stripes 802 are in the metal 2layer, second set of metal stripes 804 are in the metal 4 layer, andthird set of metal stripes 806 are in the metal 3 layer. However, othermetal layers are within scope of the disclosure. In some implementationstwo of first set of metal stripes 802, second set of metal stripes 804,and third set of metal stripes 806 can be in a same metal layer and theremaining being in a different metal layer. For example, the metalstripes of each of first set of metal stripes 802 and second set ofmetal stripes 804 can be in metal 2 layer or metal 4 layer, and thirdset of metal stripes 806 can be in metal 3 layer.

FIG. 9A illustrates a fourth example implementation 900 of first metalC1 106 and second metal capacitor C2 406 in accordance with someembodiments. Fourth example implementation 900, which is also referredto as via style, includes two sets of metal stripe. In addition, fourthexample implementation 900 includes a plurality of vias formed on themetal stripes. Each of the two set of metal stripes form twosub-capacitors. For example, a first sub-capacitor is formed from afirst set of metal stripes placed parallel to each other and a secondsub-capacitor is formed from a second set of metal stripes placedparallel to each other. Moreover, additional capacitors are formed fromthe plurality of vias. For example, each of the two adjacent vias form acapacitor between them. A capacitance value of each of the twosub-capacitors is dependent on a number of metal stripes in eachcorresponding set of metal stripes, dimensions (that is, a length, awidth, and a thickness) of the metal stripes, a number of vias in eachcorresponding set of metal stripes, and dimensions (that is, a length, awidth, and a thickness) of each vias. An overall capacitance value infourth example implementation 900 is determined as sum of the twosub-capacitors formed by the two set of metal stripes.

For example, and as shown in FIG. 9A, fourth example implementation 900includes a first set of metal stripes 902 and a second set of metalstripes 904. Each of first set of metal stripes 902 and second set ofmetal stripes 904 are in different metal layers. For example, first setof metal stripes 902 are in the metal 2 layer and second set of metalstripes 904 are in the metal 4 layer. However, other metal layers arewithin the scope of disclosure. In some implementations, each of firstset of metal stripes 902 and second set of metal stripes 904 are in asame metal layer.

Each of first set of metal stripes 902 and second set of metal stripes904 include a predetermined number of metal stripes. For example, firstset of metal stripes 902 includes three metal stripes and second set ofmetal stripes 904 includes seven metal stripes. However, a number ofmetal stripes may vary based on a desired capacitance value. Hence, adifferent number of metal stripes for each of first set of metal stripes902 and second set of metal stripes 904 is within the scope of thedisclosure.

First set of metal stripes 902 includes a first plurality of vias 906and second set of metal stripes 904 include a second plurality of vias908. Each pair of adjacent vias of first plurality of vias 906 andsecond plurality of vias 908 form a capacitor between them. Therefore, anumber of vias in each of first plurality of vias 906 and secondplurality of vias 908 can be changed to change a capacitance value offourth example implementation 900. FIG. 9B illustrates examplecross-sectional view of first metal stripes 902 including firstplurality of vias 906. As shown in FIG. 9B, first plurality of vias 906are formed in metal 3 layer. However, other metal layers are within thescope of the disclosure. FIG. 9C illustrates example cross-sectionalview of second metal stripes 904 including second plurality of vias 908.As shown in FIG. 9C, second plurality of vias 908 are formed in metal 5layer. However, other metal layers are within the scope of thedisclosure. Moreover, each of first plurality of metal stripes 902 andsecond plurality of metal stripes 904 is shown to include two rows ofvias. However, different number of rows of vias are within the scope ofthe disclosure.

Continuing with FIG. 9A, each metal stripes of first set of metalstripes 902 and second set of metal stripes 904 are connected to a firstmetal line 910 and 912 in alternate. First metal line 910 is connectedto a first node (that is, Node A) and second metal line 912 is connectedto a second node (that is, Node B). In fourth example implementation, acapacitor is formed between the Node A and the Node B. Node A and Node Bbe can be one of node 1, node 2, node 3, and node 4 of memory device100.

In addition, dimensions of each metal stripes of first set of metalstripes 902 and second set of metal stripes 904 may also may vary basedon a desired capacitance value. In example embodiments, each metalstripe of first set of metal stripes 902 are parallel to each other withgaps between the stripes being filled with a dielectric material.Similarly, each metal stripe of second set of metal stripes 904 areparallel to each other with gaps between the stripes being filled with adielectric material. Examples of the dielectric material include apolymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene(BCB), or the like; a nitride such as silicon nitride or the like; anoxide such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicateGlass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or the like; thelike, or a combination thereof. However, other dielectric materials arewithin scope of the disclosure.

In example embodiments, a length of metal stripes forming first metalcapacitor C1 106 may be varied based on a length of a bit line of cellarray 112. For example, the length of the metal stripes forming firstmetal capacitor C1 106 may be extended approximately equal to a lengthof the bit line of cell array 112. In some example, the length of themetal stripes of first set of metal stripes 702, 802, and 902 or secondset of metal stripes 704, 804, and 904 forming first metal capacitor C1106 may be extended approximately equal to a length of the bit line ofcell array 112. The extended lengths of the metal stripes may be variedto vary the capacitance value as well as an amount of power spent forthe write operations.

FIGS. 10A and 10B illustrates different lengths for the metal stripesforming first metal capacitor C1 106 in accordance with someembodiments. As illustrated in FIGS. 10A and 10B, the length of themetal stripes includes a base length 1002 and extended lengths 1004 and1006. Extended lengths 1004 and 1006 can track the length of the bitline, and hence may extend to be equal to the length of a bit line ofcell array 112. For example, and as illustrated in FIGS. 10A and 10B,extended length 1004 of FIG. 10A which is associated with a longer bitline is longer than extended length 1006 of FIG. 10B which is associatedwith a shorter bit line.

FIG. 10C illustrates a graph 1010 illustrating modeled results of usingextended length metal stripes for first metal capacitor C1 106 incomparison with using long MOS capacitor bit line boost circuit 102 fordifferent operating voltages of cell array 112. For example, first plot1012 illustrates the modeled results of base length 1002 metal stripesfor first metal capacitor C1 106, second plot 1014 illustrates themodeled results of extended lengths 1004 and 1006 metal stripes forfirst metal capacitor C1 106, third plot 1016 illustrates the modeledresults of using a base length MOS capacitor, and fourth plot 1018illustrates the modeled results of using an extended length MOScapacitor. As shown in FIG. 10C a gap between voltage values are lessfor first metal capacitors C1 106 compared to the MOS capacitor with thechange in the length of the metal stripes.

FIG. 10D illustrates a histogram 1020 of power consumption during writeoperations for cell array 112. For example, first histogram 1022illustrates a power consumption of an extended length MOS capacitor,second histogram 1024 illustrates a power consumption of a base lengthbit line MOS capacitor, a third histogram 1026 illustrates a powerconsumption of an extended length first metal capacitor C1 106, andfourth histogram 1028 illustrates a power consumption of a basic lengthfirst metal capacitor C1 106. As shown in histogram 1020, the powerconsumption for the write operations remains same with variation inlength of the MOS capacitors. However, the power consumption of extendedlength 1004 and 1006 metal stripes is higher than that of a base length1002 metal stripes for first metal capacitor C1 106.

In example embodiments, a length of metal stripes forming secondcapacitor C2 406 may be varied based on a length of a word line of cellarray 112. For example, the length of the metal stripes forming secondmetal capacitor C2 406 may be varied up to approximately equal to alength of the word line of cell array 112. In some example, the lengthof the metal stripes of first set of metal stripes 702, 802, and 902 orsecond set of metal stripes 704, 804, and 904 forming second metalcapacitor C2 406 may extended approximately equal to a length of theword line of cell array 112. The lengths of the metal stripes may bevaried to vary the capacitance value as well as an amount of power spentfor the write operations

FIGS. 11A and 11B illustrates different lengths for the metal stripesforming second metal capacitor C2 206 in accordance with someembodiments. As illustrated in FIGS. 11A and 11B, length of the metalstripes may include a base length 1102 and extended lengths 1104 and1106. Extended lengths 1104 and 1106 may be equal to a length of a wordline of cell array 112. For example, and as illustrated in FIGS. 11A and11B, extended length 1004 of FIG. 10A which is associated with a longerword line is longer than extended length 1006 of FIG. 10B which isassociated with a shorter bit line.

In example embodiments, both bit line boost circuit 102 and word lineboost circuit 402 may be used together in device 100. For example, bitline boost circuit 102 can be used to boost negative voltage of the bitline and word line boost circuit 402 may be used to substantiallysimultaneously boost the voltage of the word line of cell array 112.

In accordance with example embodiments, a write assist circuitcomprises: a transistor switch coupled between a bit line voltage nodeof a cell array and a ground node; an invertor operative to receive aboost signal responsive to a write enable signal, wherein an output ofthe invertor is coupled to a gate of the transistor switch; and a metalcapacitor having a first end coupled to the bit line voltage node and asecond end coupled to the gate of the transistor switch, wherein themetal capacitor is operative to drive a bit line voltage of the bit linevoltage node to a negative value from the ground voltage in response tothe boost signal.

In example embodiments, a write assist circuit comprises: a firsttransistor switch connected between a word line voltage node and asupply voltage, wherein a gate of the first transistor switch isoperative to receive a boost signal responsive to a write enable signal;a second transistor switch connected between the word line voltage nodeand the supply voltage, wherein a gate of the second transistor switchis coupled to the word line voltage node; and a metal capacitor having afirst end coupled to the word line voltage node and a second endoperative to receive the boost signal, wherein the metal capacitor isoperative to drive a word line voltage of the word line voltage node toa boosted value from the supply voltage in response to the boost signal.

In accordance with example embodiments a method of negatively boosting abit line voltage for writing data to a memory cell, the methodcomprises: connecting, during a write enable period, a bit line voltagenode to the ground through a first transistor switch; turning,responsive to a boost signal, the first transistor switch off todisconnect the bit line voltage node from the ground; initiating, afterthe first transistor switch is turned off, charging of a first metalcapacitor having a first end coupled to the bit line voltage node and asecond end coupled to the gate of the first transistor switch, whereincharging of the first metal capacitor drives the bit line voltage nodeto a first negative voltage; and turning, after the end of the writeenabled period, on the first transistor switch to reconnect the bit linevoltage node to the ground.

In example embodiments, a method of boosting a word line voltage forwriting data to a memory cell, the method comprises: disconnecting, at astart of a write enable period, a word line voltage node from a supplynode through a second transistor switch; turning, responsive to a boostsignal, off the first transistor switch off disconnect the word linevoltage node from the supply voltage; initiating, after the secondtransistor switch is turned off, charging of a second metal capacitorhaving a first end coupled to the word line voltage node and a secondend coupled to a gate of the second transistor switch, wherein chargingof the second metal capacitor drives the word line voltage node to aboosted voltage, the boosted voltage being higher than the supplyvoltage; and turning, after the end of the write enabled period, on thesecond transistor switch to reconnect the word line voltage node to thesupply voltage.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A write assist circuit comprising: a firsttransistor switch connected between a word line voltage node and asupply voltage, wherein a gate of the first transistor switch isoperative to receive a boost signal responsive to a write enable signal;a second transistor switch connected between the word line voltage nodeand the supply voltage, wherein a gate of the second transistor switchis coupled to the word line voltage node; and a metal capacitor having afirst end coupled to the word line voltage node and a second endoperative to receive the boost signal, wherein the metal capacitor isoperative to drive a word line voltage of the word line voltage node toa boosted value from the supply voltage in response to the boost signal.2. The write assist circuit of claim 1, wherein the boost signal isoperative to turn off the first transistor switch, initiate charging ofthe metal capacitor, and boost the word line voltage.
 3. The writeassist circuit of claim 1, further comprising a word line driver circuitoperative to provide the word line voltage to a word line of a cellarray.
 4. The write assist circuit of claim 1, further comprising ametal oxide semiconductor connected in parallel to the metal capacitor.5. The write assist circuit of claim 1, wherein the metal capacitor is ahand clasping style metal capacitor comprising a first plurality ofmetal stripes and a second plurality of metal stripes.
 6. The writeassist circuit of claim 5, wherein a length of at least one of the firstplurality of metal stripes and the second plurality of metal stripescomprises a base length and an extended length, wherein the extendedlength is less than or equal to a word line length of a cell array. 7.The write assist circuit of claim 5, wherein the first plurality ofmetal stripes are in a first metal layer and the second plurality ofmetal stripes are formed in a second metal layer, the second metal layerbeing different from the first metal layer.
 8. The write assist circuitof claim 5, wherein the first plurality of metal stripes form a firstsub-capacitor and the second plurality of metal stripes form a secondsub-capacitor, wherein the second sub-capacitor is parallel to the firstsub-capacitor.
 9. The write assist circuit of claim 8, wherein at leastone of the first sub-capacitor and the second sub-capacitor isselectively enabled.
 10. A write assist circuit comprising: a firsttransistor connected between a word line voltage node and a supplyvoltage, wherein a gate of the first transistor is operative to receivea boost signal responsive to a write enable signal; a second transistorconnected between the word line voltage node and the supply voltage,wherein a gate of the second transistor is coupled to the word linevoltage node; a third transistor connected between the word line voltagenode and the supply voltage, wherein a gate of the third transistor iscoupled to the word line voltage node, and wherein a source and a drainof the third transistor are connected together and are operative toreceive the boost signal; and a metal capacitor having a first endcoupled to the word line voltage node and a second end operative toreceive the boost signal, wherein the metal capacitor is operative todrive a word line voltage of the word line voltage node to a boostedvalue from the supply voltage in response to the boost signal.
 11. Thewrite assist circuit of claim 10, further comprising a word line drivercircuit operative to provide the word line voltage to a word line of acell array.
 12. The method of claim 10, wherein the first metalcapacitor is a hand clasping style metal capacitor comprising a firstplurality of metal stripes and a second plurality of metal stripes. 13.The method of claim 12, wherein a length of at least one of the firstplurality of metal stripes and the second plurality of metal stripescomprises a base length and an extended length, wherein the extendedlength is less than or equal to a word line length of a cell array. 14.The method of claim 12, wherein the first plurality of metal stripes arein a first metal layer and the second plurality of metal stripes areformed in a second metal layer, the second metal layer being differentfrom the first metal layer.
 15. The method of claim 12, wherein thefirst plurality of metal stripes form a first sub-capacitor and thesecond plurality of metal stripes form a second sub-capacitor, whereinthe second sub-capacitor is parallel to the first sub-capacitor.
 16. Awrite assist circuit comprising: a first transistor connected between aword line voltage node and a supply voltage, wherein a gate of the firsttransistor is operative to receive a boost signal responsive to a writeenable signal; a second transistor connected between the word linevoltage node and the supply voltage, wherein a gate of the secondtransistor is coupled to the word line voltage node; a third transistorconnected between the word line voltage node and the supply voltage,wherein a gate of the third transistor is coupled to the word linevoltage node, and wherein a source and a drain of the third transistorare connected together and are operative to receive the boost signal;and a first metal capacitor comprising a first plurality of metalstripes substantially parallel to each other and a second plurality ofmetal stripes substantially parallel to each other, wherein the firstplurality of metal stripes are coupled to the word line voltage node,wherein the second plurality of metal stripes are operative to receivethe boost signal, wherein the metal capacitor is operative to drive aword line voltage of the word line voltage node to a boosted value fromthe supply voltage in response to the boost signal.
 17. The write assistcircuit of claim 16, wherein the first metal capacitor is a handclasping style metal capacitor.
 18. The write assist circuit of claim16, wherein the first plurality of metal stripes are in a first metallayer and the second plurality of metal stripes are formed in a secondmetal layer, the second metal layer being different from the first metallayer.
 19. The write assist circuit of claim 16, wherein the firstplurality of metal stripes form a first sub-capacitor and the secondplurality of metal stripes form a second sub-capacitor, wherein thesecond sub-capacitor is parallel to the first sub-capacitor.
 20. Thewrite assist circuit of claim 19, wherein at least one of the firstsub-capacitor and the second sub-capacitor is selectively enabled.